1. Field of the Invention
This invention relates generally to substrate fabrication, and more particularly to semiconductor wafer cleaning after etch operations.
2. Description of the Related Art
As is well known, semiconductor devices are fabricated from semiconductor wafers, which are subjected to numerous processing operations. These operations include, for example, impurity implants, gate oxide generation, inter-metal oxide depositions, metallization depositions, photolithography pattering, etching operations, chemical mechanical polishing (CMP), etc.
To facilitate discussion, FIG. 1 illustrates a cross-section view of a layer stack, representing the layers formed during the fabrication of a typical semiconductor integrated circuit (IC) device. It should be noted that additional layers above, below, or between the layers shown may be present. Further, not all of the illustrated layers need necessarily be present and some or all may be substituted by a variety of different layers.
At the bottom of the layer stack, there is shown a substrate 10. An oxide layer 11 which is typically a silicon dioxide (SiO.sub.2) is shown formed over the surface of the substrate 10. A barrier layer 12, typically formed of Ti, TiW, TiN or other suitable barrier materials, may be disposed between oxide layer 11 and a subsequently deposited metallization layer 13. Barrier layer 12, when provided, functions to substantially prevent diffusion of silicon atoms from oxide layer 11 and into the metallization layer 13.
Metallization layer 13 typically includes aluminum, copper or one or more of a variety of known aluminum alloys such as Al--Cu, Al--Si, and Al--Cu--Si. Also shown is an anti-reflective coating (ARC) layer 14 that is formed over metallization layer 13. As is well known in the art, ARC layer 14 is typically composed of Ti, TiN or TiW. Generally speaking, ARC layer 14 is useful in preventing light used in photolithography processes from reflecting and scattering off of the metallization layer 13 surface. Another oxide layer 16 is then formed over the ARC layer 14. In this simplified example, a photoresist layer 18 is then spin coated over the oxide layer 16 and patterned to define windows where etching is desired. As is well known, photoresist layer 18 represents a layer of conventional photo-sensitive resist material that may be patterned using patterned reticles and a stepper that passes selective light waves onto the surface of photoresist layer 18. The layers of the layer stack are readily recognizable to those skilled in the art and may be formed using any number of known deposition processes, including chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), physical vapor deposition (PVD) such as sputtering, spin coating, etc.
At this point, an etch operation 20 is performed in order to selectively remove portions of the oxide 16. In this example, a feature 17 is etched into the oxide 16, and the feature 17 may be a trench, a via hole, or any other geometric pattern. Preferably, the etch 20 is chosen to have good selectivity to enable efficient etching of the oxide 16. During the etching operation, however, polymer formation 22 is known to occur on the sidewalls of features 17 being etched. This polymer formation 22, as shown, typically takes on the shape of a crown or a veil. This shape therefore is observed to extend along the sidewalls and up onto the photoresist layer 18.
The actual composition of the polymer formation 22 depends upon the material being etched, the chemistry used for the etching, and the underlying material (e.g., the ARC layer 14). Although there are many types of chemistries used to plasma etch through an oxide layer 16, typical chemistries may include CF.sub.4 and O.sub.2, NF.sub.3, and C.sub.4 F.sub.8 among others. Thus, the material representing the polymer formation 22 will generally be an oxide material containing some of the etch chemistry components, carbon from the photoresist, and metallization material (e.g., Ti, TiN, Al, Si, and Cu) from the ARC layer 14 and the metal layer 13.
After the plasma etching is performed, the conventional process is to perform what is referred to as an ashing operation to remove the photoresist layer 18. This ashing operation may remove some of the polymer formation 22, however, most may still remain on the sidewalls of the etched oxide layer 16. To remove this remaining polymer formation 22, it is conventional practice to move the wafer into a chemical bath containing liquids that are designed to remove the polymer formation 22. An example chemical bath may include a chemical referred to as EKC-265, which is available from EKC, Inc. of Hayward, Calif.
Although chemical bath rinsing has worked in the past, the demand for smaller device features has increased the need to have a very clean environment at every step of a fabrication process. Unfortunately, bath rinsing is inherently an unclean environment. Polymer material being rinsed in the bath may therefore contaminate the bath, and the removed material may be deposited or can attach to other parts of a wafer or to other wafers being processed through the bath. In some cases, the polymer formation 22 material may become lodged at the base of an etched feature, and due to its oxide composition, the material may prevent electrical contact through that feature (e.g., once a next metal formation step is performed to fill the oxide etched feature). Accordingly, surface particles and contaminants can detrimentally impact the performance of an integrated circuit device.
In view of the foregoing, there is a need for improved methods that will enable efficient removal of post plasma etch polymer materials from etched features. The removal should be efficient enough to remove the polymer material and prevent further contamination of other surface areas of a wafer being processed.